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?2005 fairchild semiconductor corporation www.fairchildsemi.com rev.1.0.2 features ? pulse by pulse current limit ? over load protection (olp) - latch ? over voltage protection (ovp) - latch ? internal thermal shutdown (tsd) - latch ? under voltage lock out (uvlo) with hysteresis ? internal high voltage sensefet (800v rated) ? user defined soft start ? precision fixed operating frequency (66khz) application ? pc power supply ?pdp description the fairchild power switch fs7m-series is an integrated pulse width modulator (pwm) and sense fet specifically designed for high performance offline switch mode power supplies (smps) with minimal external components. this device is an integrated high voltage power switching regulator which combine an avalanche rugged sense fet with a current mode pwm control block. the pwm controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (leb), optimized gate driver, soft start, temperature compen sated precise current sources for a loop compensation and self protection circuitry. compared with discrete mosfet and pwm controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. this device is a basic platform well suited for cost effective designs of flyback and forward converters. table 1. maximum output power notes: 1. maximum practical continuous power in an open frame design at 50 c ambient. 2. 230 vac or 100/115 vac with doubler. 3. when the cooling fan is used. typical circuit figure 1. typical for ward application output power table product 230vac 15% (2) 85-265vac open frame (1) open frame (1) fs7m0680 80w (flyback) 150w (forward) 180w (forward) (3) 65w (flyback) fs7m0880 110w (flyback) 200w (forward) 250w (forward) (3) 85w (flyback) vcc gnd drain s/s vo pwm v fb ac in fs7m-series fs7m0680, fs7m0880 fairchild power switch (fps tm )
fs7m0680, fs7m0880 2 internal block diagram figure 2. functional block diagram of fs7m0680 and fs7m0880 9v/15v 3 1 2 4 5 vref internal bias s q q r osc vcc vref i delay i fb v sd tsd vovp vcc vocp s q q r r 2.5r vcc reset (vcc<6v) vcc drain soft start fb gnd aocp gate driver vcc good leb pwm vref reset
fs7m0680, fs7m0880 3 pin definitions pin configuration figure 3. pin configuration (top view) pin number pin name pin function description 1 drain high voltage power sensefet drain connection. 2 gnd this pin is the control ground and the sensefet source. 3vcc this pin is the positive supply input. this pin provides internal operating current for both start-up and steady-state operation. 4vfb this pin is internally connected to the inverting input of the pwm comparator. the collector of an opto-coupler is typically tied to this pin. for stable operation, a capacitor should be placed between this pin and gnd. if the voltage of this pin reaches 7.5v, the over load protection triggers resulting in shutdown of the fps. 5 soft-start this pin is for the soft start. soft start time is programmed by a capacitor on this pin. 5.s/s 4.vfb 3.vcc 2.gnd 1.drain to-3p-5l
fs7m0680, fs7m0880 4 absolute maximum ratings note: 1. t j = 25 c to 150 c 2. repetitive rating: pulse width limi ted by maximum junction temperature 3. l = 24mh, v dd = 50v, r g = 25 ? , starting tj =25 c 4. l = 13 h, starting t j = 25 c fs7m0680 parameter symbol value unit maximum drain voltage (1) v d,max 800 v drain-gate voltage (r gs =1m ? )v dgr 800 v gate-source (gnd) voltage v gs 30 v drain current pulsed (2) i dm 24.0 a dc single pulsed avalanche energy (3) e as 455 mj avalanche current (4) i as 20 a continuous drain current (t c =25 c) i d 6.0 a dc continuous drain current (t c =100 c) i d 3.8 a dc maximum supply voltage v cc,max 30 v input voltage range v fb -0.3 to v sd v total power dissipation p d 150 w derating 1.21 w/ c operating ambient temperature t a -25 to +85 c storage temperature t stg -55 to +150 c fs7m0880 parameter symbol value unit maximum drain voltage (1) v d,max 800 v drain-gate voltage (r gs =1m ? )v dgr 800 v gate-source (gnd) voltage v gs 30 v drain current pulsed (2) i dm 32.0 a dc single pulsed avalanche energy (3) e as 810 mj avalanche current (4) i as 15 a continuous drain current (t c =25 c) i d 8.0 a dc continuous drain current (t c =100 c) i d 5.6 a dc maximum supply voltage v cc,max 30 v input voltage range v fb -0.3 to v sd v total power dissipation p d 190 w derating 1.54 w/ c operating ambient temperature t a -25 to +85 c storage temperature t stg -55 to +150 c
fs7m0680, fs7m0880 5 electrical characteristics (sensefet part) (ta=25 c unless otherwise specified) note: 1. pulse test: pulse width 300 s, duty cycle 2% fs7m0680 parameter symbol condition min. typ. max. unit drain-source breakdown voltage bv dss v gs =0v, i d =50 a 800 - - v zero gate voltage drain current i dss v ds =max., rating, v gs =0v --50 a v ds =0.8max., rating, v gs =0v, t c =125 c - - 200 a static drain-source on resistance (note1) r ds(on) v gs =10v, i d =5.0a - 1.6 2.0 ? input capacitance ciss v gs =0v, v ds =25v, f=1mhz - 1600 - pf output capacitance coss - 140 - reverse transfer capacitance crss - 42 - turn on delay time td(on) v dd =0.5bv dss , i d =8.0a (mosfet switching time are essentially independent of operating temperature) -60- ns rise time tr - 150 - turn off delay time td(off) - 300 - fall time tf - 130 - total gate charge (gate-source+gate-drain) qg v gs =10v, i d =8.0a, v ds =0.5bv dss (mosfet switching time are essentially independent of operating temperature) -70- nc gate-source charge qgs - 16 - gate-drain (miller) charge qgd - 27 - fs7m0880 parameter symbol condition min. typ. max. unit drain-source breakdown voltage bv dss v gs =0v, i d =50 a 800 - - v zero gate voltage drain current i dss v ds =max., rating, v gs =0v --50 a v ds =0.8max., rating, v gs =0v, t c =125 c - - 200 a static drain-source on resistance (note1) r ds(on) v gs =10v, i d =5.0a - 1.2 1.5 ? input capacitance ciss v gs =0v, v ds =25v, f=1mhz - 2460 - pf output capacitance coss - 210 - reverse transfer capacitance crss - 64 - turn on delay time td(on) v dd =0.5bv dss , i d =8.0a (mosfet switching time are essentially independent of operating temperature) --90 ns rise time tr - 95 200 turn off delay time td(off) - 150 450 fall time tf - 60 150 total gate charge (gate-source+gate-drain) qg v gs =10v, i d =8.0a, v ds =0.5bv dss (mosfet switching time are essentially independent of operating temperature) - - 150 nc gate-source charge qgs - 20 - gate-drain (miller) charge qgd - 70 -
fs7m0680, fs7m0880 6 electrical characteristics (continued) (ta=25 c unless otherwise specified) note: 1. these parameters, although guaranteed, are not 100% tested in production 2. these parameters, although guaranteed, ar e tested in eds (wafer test) process parameter symbol condition min. typ. max. unit uvlo section start threshold voltage v start - 14 15 16 v stop threshold voltage v stop after turn on 8 9 10 v oscillator section initial frequency f osc - 606672khz frequency change with temperature (2) ? f/ ? t-25 c ta +85 c- 5 10 % maximum duty cycle dmax - 45 50 55 % feedback section feedback source current i fb ta=25 c, 0v vfb 3v 0.7 0.9 1.1 ma shutdown delay current idelay ta=25 c, 5v vfb v sd 4.0 5.0 6.0 a soft start section soft start voltage v ss v fb =2v 4.7 5.0 5.3 v soft start current i ss sync & s/s=gnd 0.8 1.0 1.2 ma current limit (selt-protection)section fs7m0680 i over max. inductor current 3.52 4.00 4.48 a fs7m0880 i over max. inductor current 4.40 5.00 5.60 a protection section thermal shutdown temperature (tj) (1) t sd - 140 c over voltage protection voltage v ovp - 25 28 31 v over current protection voltage v ocp - 1.05 1.10 1.15 v total device section start up current i start v cc =14v - 40 80 ua operating supply current (control part only) i op ta=25 c-812ma iop(lat) after latch, vcc=vstop-0.1v 150 250 350 ua shutdown feedback voltage v sd - 6.9 7.5 8.1 v
fs7m0680, fs7m0880 7 electrical characteristics -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40-20 0 20406080100120140160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 operating supply current vs. temp. temperature [ c] temperature [ c] temperature [ c] temperature [ c] temperature [ c] normalized to 25 c normalized to 25 c normalized to 25 c normalized to 25 c dmax [%] start up current vs. temp. vcc start threshold voltage vs. temp. vcc stop threshold voltage vs. temp. operating frequency vs. temp. maximum duty cycle vs. temp. temperature [ c] normalized to 25 c -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20
fs7m0680, fs7m0880 8 electrical characteristics -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40 -20 0 20 40 60 80 100 120 140 160 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -40-20 0 20406080100120140160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 temperature [ c] temperature [ c] temperature [ c] temperature [ c] temperature [ c] temperature [ c] normalized to 25 c normalized to 25 c normalized to 25 c normalized to 25 c normalized to 25 c normalized to 25 c minimum duty cycle vs. temp. feedback offset voltage vs. temp. shutdown feedback voltage vs. temp. shutdown delay current vs. temp. softstart voltage vs. temp. over voltage protection vs. temp.
fs7m0680, fs7m0880 9 electrical characteristics -40 -20 0 20 40 60 80 100 120 140 160 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -40 -20 0 20 40 60 80 100 120 140 160 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 temperature [ c] temperature [ c] normalized to 25 c normalized to 25 c feedback current vs. temp. pulse-by-pulse current limit vs. temp.
fs7m0680, fs7m0880 10 functional description 1. startup : figure 4 shows the typical startup circuit and transformer auxiliary winding for fs7m-series. because all the protections are implemented as latch mode, ac startup is typically used to provide a fast reset as shown in figure 4. before fps begins switching operation, only startup current (typically 40ua) is consumed and the current supplied from the ac line charges the external capacitor (c a ) that is connected to the vcc pin. when vcc reaches start voltage of 15v (v start ), fps begins switching, and the current consumed by fps increases to 8ma. then, fps continues its normal switching operation and the power required for this device is supplied from the transformer auxiliary winding, unless vcc drops below the stop voltage of 9v (v stop ). to guarantee the stable operation of the control ic, vcc has under voltage lockout (uvlo) with 6v hysteresis. figure 5 shows the relation between the fps operating supply current and the supply voltage (vcc). figure 4. startup circuit figure 5. relation between ope rating supply current and vcc voltage the minimum average of the current supplied from the ac is given by where v ac min is the minimum input voltage, v start is the vcc start voltage (15v) and r str is the startup resistor. the startup resistor should be chosen so that i sup avg is larger than the maximum startup current (80ua). once the resistor value is determined, the maximum loss in the startup resistor is obtained as where v ac max is the maximum input voltage. the startup resistor should have proper rated dissipation wattage. 2. feedback control : fs7m-series employs current mode control, as shown in figure 6. an opto-coupler (such as the h11a817a) and shunt regulator (such as the ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. when the reference pin voltage of the ka431 exceeds the internal reference voltage of 2.5v, the h11a817a led current increases, thus pulling down the feedback voltage and reducing the duty cycle. this event typically happens when the input voltage is increased or the output load is decreased. 2.1 pulse-by-pulse current limit : because current mode control is employed, the peak current through the sense fet is limited by the inverting input of pwm comparator (vfb*) as shown in figure 6. the feedback current (i fb ) and internal resistors are designed so that the maximum cathode voltage of diode d 2 is about 2.8v, which occurs when all i fb flows through the internal resistors. since d 1 is blocked when the feedback voltage (vfb) exceeds 2.8v, the maximum voltage of the cathode of d2 is clamped at this voltage, thus clamping vfb*. therefore, the peak value of the current through the sense fet is limited. 2.2 leading edge blanking (leb) : at the instant the internal sense fet is turned on, there usually exists a high current spike through the sense fet, caused by external resonant capacitor across the mosfet and secondary-side rectifier reverse recovery. excessive voltage across the r sense resistor would lead to incorrect feedback operation in the current mode pwm control. to counter this effect, the fps employs a leading edge blanking (leb) circuit. this circuit inhibits the pwm comparator for a short time (t leb ) after the sense fet is turned on. fs7m -se rie s 1n4007 rstr vcc c a da i sup ac line (v ac min - v ac max ) c dc icc vcc vstop=9v 40ua 8ma vstart=15v vz power up power down i sup avg 2v ac min ? ----------------------------- - v start 2 -------------- ? ?? ?? ?? 1 r str ---------- ? = loss 1 r str --------- - v ac max () 2 v start 2 + 2 --------------------------------------------------- 22v start v ac max ?? ----------------------------------------------------- - ? ?? ?? ?? ? =
fs7m0680, fs7m0880 11 figure 6. pulse width m odulation (pwm) circuit 3. protection circuit : the fs7m-series has several self protective functions such as over load protection (olp), abnormal over current protection (aocp), over voltage protection (ovp) and thermal shutdown (tsd). all the protections are latch mode protection. because these protection circuits are fully integrated into the ic without external components, the reliability can be improved without increasing cost. once protection triggers, switching is terminated and vcc continues charging and discharging between 9v and 15v until the ac power line is un-plugged. the latch is reset only when vcc is fully discharged by un-plugging the ac power line. figure 7. auto restart mode protection 3.1 over load protection (olp) : overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. in this situation, the protection circuit should trigger in order to protect the smps. however, even when the smps is in the normal operation, the over load protection circuit can be triggered during the load transition. in order to avoid this undesired operation, the over load protection circuit is designed to trigger after a specified time to determine whether it is a transient situation or an overload situation. because of the pulse-by-pulse current limit capability, the maximum peak current through the sense fet is limited, and therefore the maximum input power is restricted with a given input voltage. if the output consumes more than this maximum power, the output voltage (vo) decreases below the set voltage. this reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (vfb). if vfb exceeds 2.8v, d1 is blocked and the 5ua current source starts to charge c b slowly up to vcc. in this condition, vfb continues increasing until it reaches 7.5v, when the switching operation is terminated as shown in figure 8. the delay time for shutdown is the time required to charge c b from 2.8v to 7.5v with 5ua. in general, a 20 ~ 50 ms delay time is typical for most applications. this protection is implemented in auto restart mode. figure 8. over load protection 3.2 abnormal over current protection (aocp) : when the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the sensefet during the leb time. even though the fs7m-series has olp (over load protection), it is not enough to protect the fps in that abnormal case, since sever current stress will be imposed on the sensefet until olp triggers. the fs7m-series has an internal aocp (abnormal over current protection) circuit as shown in figure 9. when the gate turn-on signal is applied to the power sense fet, the aocp block is enabled and monitors the current through the sensing resistor. the voltage across the resistor is then 4 osc vcc vref i delay i fb v sd r 2.5r gate driver olp d1 d2 + v fb * - vfb ka431 c b vo h11a817a r sense sensefet latch 9v 15v vcc vds t fault occurs normal operation ac line un-plugged vcc reset ac line plugged-in ac line plugged-in 6v normal operation v fb t 2.8v 7.5v over load protection t 12 = c b *(7.5-2.8)/i delay t 1 t 2
fs7m0680, fs7m0880 12 compared with a preset aocp level. if the sensing resistor voltage is greater than the aocp level, the set signal is applied to the latch, resulting in the shutdown of smps. this protection is implemented in latch mode. figure 9. aocp block 3.3 over voltage protection (ovp) : if the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. then, vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the smps until the over load protection is activated. because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. in order to prevent this situation, an over voltage protection (ovp) circuit is employed. in general, vcc is proportional to the output voltage and the fps uses vcc instead of directly monitoring the output voltage. if v cc exceeds 28v, an ovp circuit is activated resulting in the termination of the switching operation. in order to avoid undesired activation of ovp during normal operation, vcc should be designed to be below ovp threshold. 3.4 thermal shutdown (tsd) : the sensefet and the control ic are built in one pack age. this makes it easy for the control ic to detect the abnormal over temperature of the sensefet. when the temperature exceeds approximately 150 c, the thermal shutdown triggers. this protection is implemented in latch mode. 4. soft start : the fs7m-series has a soft start circuit that increases pwm comparator inve rting input voltage together with the sensefet current slowly after it starts up. the soft start time can be programmed using a capacitor on the soft- start pin. the pulse width to the power switching device is progressively increased to es tablish the correct working conditions for transformers, induc tors, and capacitors. it also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 2 s q q r osc r 2.5r gnd gate driver leb pwm + - vaocp aocp r sense
fs7m0680, fs7m0880 13 typical application circ uit i (7m0880 : forward) 1. schematic 2.transformer specification ( core : eer 3542 , bobbin : eer3542 ) transformer electrical characteristics 3. secondary induct or(l1) specification core : power core 27 16 grade 5v : 12t (1 2) 10v : 27t (1.2 1) application output power input volt age output voltage (max current) pc power 250w (cooling fan) universal input with voltage doubler 5v (26a), 12v (10a) no. pin(s f) wire turns winding method n p/2 1 30.65 1 50t solenoid winding n+5v 8, 9 10, 11, 12 15mm 0.15mm 1 4t copper foil winding n+12v 13, 14 90.65 3 5t solenoid winding n p/2 1 30.65 1 50t solenoid winding n vcc 7 60.6 1 6t solenoid winding pin specification remarks inductance 1 - 3 6mh 5% @70khz, 1v leakage inductance 1 - 3 15uh max 2 nd all short t1 eer3542 c6 22nf 630v 1 6 r1 50k ? 0.5w r4 56k ? 2w d2 fr257 c9 33nf c7 33uf 35v d3 uf4007 r7 10 ? r11 1k ? r12 820 ? c17 100nf r10 1k ? op1 pc817 ic3 ka431 3 7 ic1 fs7m0880 c15 10nf 1kv f101 fuse 250v 5.0a lf1 c1 470nf 275vac c4 470uf 200v c2 4.7nf 1kv c10 1uf 16v bd1 gdb206 fb vcc drain gnd 1 2 3 4 s/s 5 rt1 10d- 11 c3 4.7nf 1kv c5 470uf 200v r6 220k ? 1w r5 220k ? 1w r3 56k ? 2w r2 50k ? 0.5w d1 uf4007 8, 9 13,14 d5 mbrf30h100ct c11 1000uf 16v l1 12v, 10a 10,11,12 d4 mbr3060pt c12 2200uf 16v c18 r13 c13 3300uf 10v c14 1000uf 10v 5v, 26a r9 1k ? c16 10nf 1kv
fs7m0680, fs7m0880 14 typical application circ uit ii (7m0880 : flyback) 1. schematic 2. transformer specification winding specification electrical characteristic core & bobbin core : eer 4042 , bobbin : eer4042 application output power input volt age output voltage (max current) adaptor 108w european input 12v (9a) no. pin(s f) wire turns winding method n p/2 1 30.4 1 42 solenoid winding insulation : polyester tape t = 0.050mm, 1layer n+12v 12 13 14mm 0.15mm 1 8 copper winding insulation : polyester tape t = 0.050mm, 3layer n b 8 70.3 1 9 solenoid winding insulation : polyester tape t = 0.050mm, 1layer n p/2 3 40.4 1 42 solenoid winding outer insulation : polyester tape t = 0.050mm, 3layer closure pin spec. remarks inductance 1 - 4 700uh 10% 1khz, 1v leakage l 1 - 4 10uh max. 2nd all short eer4042 12 13 m br30100ct 2200uf / 25v x3 2200uf 25v 9uh 12v, 9a 22nf 630v 1 3 7 100k ? 1w 47k ? 2w uf 4007 22nf 47uf 50v uf4004 12 ? 1k ? 2.2k ? 7.6k ? 47nf 1k ? pc817 ic3 ka431 4 8 ic1 fs7m 0880 3.3nf fuse 250v 2.0a lf1 20mh 100nf 275vac 100uf 400v ntc 10d- 11 2.2nf 250vac 2.2nf 250vac 1uf 50v 2kbp06m3n257 4.7k ? fb vcc drain gnd 1 2 3 4 s/s 5
fs7m0680, fs7m0880 15 package dimensions to-3p-5l
fs7m0680, fs7m0880 16 package dimensions (continued) to-3p-5l(forming)
fs7m0680, fs7m0880 17 ordering information tu : non forming type ydtu : forming type product number package rating fosc fs7m0680tu to-3p-5l 800v, 6a 66khz fs7m0680ydtu to-3p-5l(forming) FS7M0880TU to-3p-5l 800v, 8a 66khz fs7m0880ydtu to-3p-5l(forming)
fs7m0680, fs7m0880 5/4/05 0.0m 001 ? 2005 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain li fe, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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